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News from JPD Laboratory

Mighty. TINY.

July 20, 2017

Dual N-channel MOSFET

• Application : DC / DC Converter
• Integrates high-side MOSFET and low-side
• MOSFET in a PowerPAK 5×6 PKG with a 50% smaller mounting area.
• By setting the low-side MOSFET to a flip structure, TAB becomes GND, allowing highly efficient heat dissipation.
• The parasitic inductance is reduced by the pin arrangement considering optimal placement of passive components.
• Combined with high performance MOSFET process, the design achieves high efficiency and high power density.
• Halogen-free / RoHS compliant (EU RoHS / UL-94 V-0 / MSL : Level 1)

DrMOS

• Application: DC / DC converter
• Integrates 3 Die: a gate driver, a high-side
• MOSFET and a low-side MOSFET in a QFN 5 × 6 package to reduce parasitic inductance.
• Flip package structure to take superior heat dissipation feature of the low-side MOSFET.
• With built-in highly accurate current and temperature detection circuit, it allows outputs to monitor both.
• Other built-in protection functions include UVLO / OCP / OTP.

CSP MOSFET

• Application: lithium ion battery
• Integrates two MOSFET in one chip
• A very thin product with only 100 um
• Ultra low resistance with advanced wafer process
• Pb-Free, Halogen-free / RoHS compliant (EU RoHS / UL-94 V-0 / MSL : Level 1)